1. Field of the Invention
The present invention relates to a filter device designed by charge domain operations (hereinafter, called a charge domain filter device).
2. Description of the Related Art
In a wireless communication SoC (System On Chip) in which a RF (Radio Frequency) circuit and a digital circuit are integrated on a single chip using a CMOS (Complementary Metal Oxide Semiconductor) technique, it is known to accomplish filtering or decimation using current mode sampling at a high clock rate or an analog discrete-time signal processing technique such as a switched capacitor circuit whereby a small-sized low-power RF circuit is realized (see, for example, L. Richard Carley and Tamal Mukherjee, “High-Speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture,” Proceedings of IEE 1995, Custom Integrated Circuits Conference, pp 543-546, May 1995).
For example, it is known to realize a SINC filter circuit having a frequency characteristic given by a SINC function by using a charge domain filter circuit configured using a transconductor and switches without using an operational amplifier (see, for example, J. Yuan, “A Charge Sampling Mixer with Embedded Filter Function for Wireless Applications”, Proceedings of IEEE 2000 International Conference on Microwave and Millimeter Wave Technology, pp. 315-318, September, 2000). An example of a charge domain filter circuit functioning as a SINC filter circuit according to a conventional technique is described below with reference to FIG. 10. In the example shown in FIG. 10, the charge domain filter circuit 10 functioning as a SINC filter circuit includes a transconductor 12, a first switch 14, a second switch 16, a third switch 18, and capacitors 20a, 20b, 20c, and 20d. 
FIG. 11 is a timing chart associated with a clock signal applied to the charge domain filter circuit 10 shown in FIG. 10. The first switch 14, the second switch 16, and the third switch 18 in the charge domain filter circuit 10 operate respectively in accordance with clock signals φ1, φ2, φ3, and φ4 which are different in phase as shown in FIG. 11.
The transconductor 12 outputs a current proportional to the voltage of a signal input to the transconductor 12.
The current output from the transconductor 12 is supplied to a capacitor selected by the first switch 14 whereby the capacitor is charged. More specifically, in the charge domain filter circuit 10 shown in FIG. 10, the first switch 14 sequentially switches its terminals in accordance with four clock signals φ1, φ2, φ3, and φ4 whereby the respective capacitors are sequentially charged.
The second switch 16 is for sequentially selecting capacitors to be sequentially reset to remove residual charges therefrom. More specifically, in the charge domain filter circuit 10 shown in FIG. 10, the second switch 16 sequentially selects its terminals in accordance with the four clock signals φ1, φ2, φ3, and φ4 whereby capacitors are sequentially selected and grounded thereby sequentially removing residual charges from the respective capacitors such that no charges originating from a previous signal remain therein.
The third switch 18 is for sequentially selecting capacitors from which to sequentially output charges stored therein to a circuit disposed at a following stage. More specifically, in the charge domain filter circuit 10 shown in FIG. 10, the third switch 18 sequentially selects its terminals in accordance with the four clock signals φ1, φ2, φ3, and φ4 whereby charges stored in the respective capacitors are sequentially output to the circuit disposed at the following stage.
In the first switch 14, the second switch 16, and the third switch 18, each terminal is labeled φ1, φ2, φ3, or φ4 to indicate a clock signal by which the terminal is selected. For example, a terminal label φ1 is selected when the clock signal φ1 is applied, a terminal label φ2 is selected when the clock signal φ2 is applied, and so on.
The current proportional to the voltage of the input signal is output from the transconductor 12 and is applied to one capacitor selected by the first switch 15 for a period of time t. In the charge domain filter circuit 10, after the selected capacitor has been charged for the period t, the resultant charge stored in the selected capacitor is output to the circuit at the following stage and sampled. For example, the first capacitor 20a is charged by the current output from the transconductor 12 via the first switch 14 controlled by the clock signal φ1, and the charge stored in this first capacitor 20a is output to the circuit at the following stage via the third switch 18 controlled by the clock signal φ2. The first capacitor 20a is then grounded via the second switch controlled by the clock signal φ4 such that the residual charge remaining in the first capacitor 20a is removed.
The capacitors 20a, 20b, 20c, and 20d are sequentially charged and discharged by the first switch 14, the second switch 16, and the third switch 18 whereby sampling is performed repeatedly with a sampling time of t. Because the input signal is sampled in a rectangular-shaped time window of t, the charge domain filter circuit 10a has a frequency characteristic such as that shown in FIG. 12. As shown in FIG. 12, the frequency characteristic of the charge domain filter circuit 10 is similar to a SINC function, and thus this circuit is called a SINC filter circuit.